Connected successfully Announcements || SNS Courseware
Menu
Subject Details
Dept     : ECE
Sem      : 5
Regul    : 2019
Faculty : T.G.Ramabharathi
phone  : NIL
E-mail  : rbharathi.tg.ece@snsce.ac.in
223
Page views
37
Files
6
Videos
2
R.Links

Icon
Announcements

  • Puzzles

    Dear Students the Puzzles has been uploaded for the following topics:</br>VLSI Testing

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br>Need for testing, </br>Basic concepts- identifiers- gate primitives, </br>Test benches, </br>gate delays, operators, timing controls, </br>Chip and system level design techniques, </br>System level test techniques., </br>Design hierarchies, </br>Design strategies for test, </br>Manufacturing test principles

  • Puzzles

    Dear Students the Puzzles has been uploaded for the following topics:</br>Pseudo NMOS Logic

  • Question Bank

    Dear Students the Question Bank has been uploaded for the following topics:</br>CMOS

  • Announcement

    Hi Guys,Welcome to new Academic year,I uploaded Syllabus and Question bank for your reference.Make use of it

  • Puzzles

    Dear Students the Puzzles has been uploaded for the following topics:</br>CMOS

  • Resource Link

    Dear Students the Resource Link has been uploaded for the following topics:</br>MOS Transistor Principle

  • Announcement*

    Dear Students the Announcement* has been uploaded for the following topics:</br>CMOS fabrication – p-well process

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br>Synchronous and Asynchronous design., </br>Synchronous and Asynchronous design., </br>Static Latches , </br>Static Registers

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br>Pseudo NMOS logic, </br>static CMOS design, </br> dynamic CMOS design, </br>Domino Logic, </br>Power dissipation, </br>Examples of Combinational Logic Design

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br>static CMOS design, </br>Power dissipation, </br>Examples of Combinational Logic Design, </br> dynamic CMOS design

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br>Pass transistor Logic, </br>Transmission gates, </br>Examples of Combinational Logic Design, </br>Static Latches

  • Youtube Video

    Dear Students the Youtube Video has been uploaded for the following topics:</br>Twin-Tub</br>VI Characteristics

  • Puzzles

    Dear Students the Puzzles has been uploaded for the following topics:</br>MOS Transistor

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br>clock strategie, </br>Timing issues

  • Puzzles

    Dear Students the Puzzles has been uploaded for the following topics:</br>Mos Transistor principle

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br>CMOS fabrication – p-well process, </br>n-well process, </br>twin-tub process, </br>MOS transistor theory-IV characteristics, </br>Non-ideal IV effects, </br>CMOS inverter , </br>DC characteristics, </br>Stick diagram, Layout diagrams., </br>CV characteristics, </br>Pass transistor Logic, </br>Transmission gates, </br>Examples of Combinational Logic Design

  • Youtube Video

    Dear Students the Youtube Video has been uploaded for the following topics:</br> P-WELL Process</br> Enhancement and Depletion mode of Transistor </br>N-WELL Process</br>Twintub process</br>Stick Diagram

  • Assignment

    Assignment topic is Design of Combinational logic Circuits and due date is 16-09-2024.

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br>Examples of Combinational Logic Design, </br>Pass transistor Logic, </br>Static Latches

  • Announcement*

    Dear Students the Announcement* has been uploaded for the following topics:</br>n-well process, </br>twin-tub process, </br>MOS transistor theory-IV characteristics, </br>CV characteristics, </br>DC characteristics, </br>Stick diagram, Layout diagrams., </br>CMOS inverter , </br>Non-ideal IV effects