UNIT 1:
Bias and Bias Stability. Various biasing Schemes/circuits and Analysis -2
Bias and Bias Stability. Various biasing Schemes/circuits and Analysis
FETs: Junction field effect transistor (JFET)
Common collector -Configurations, I-V Characteristics
Common emitter -Configurations, I-V Characteristics
Common Base -Configurations, I-V Characteristics
BJTs : Transistor in equilibrium (no external bias). Transistor with external bias, Transistor Action. Efficiency Factors
MOSFETs :Depletion MOSFET
Enhancement MOSFET; Biasing of MOSFETs.
UNIT 2:
Basics of LC & RC oscillatory circuit
UNIT 3:
Boolean expression - Minimization of Boolean expressions -- Minterm Maxterm
Sum of Products (SOP) - Product of Sums (POS)
Karnaugh map Minimization
AND, OR, NOT, NAND, NOR, Exclusive-OR and Exclusive-NOR
Implementations of Logic Functions using gates
Boolean expression - Minimization of Boolean expressions -- Minterm Maxterm
Boolean expression - Minimization of Boolean expressions -- Minterm Maxterm
UNIT 4:
Design procedure - Half adder - Full Adder
Half subtractor - Full subtractor
Parallel binary adder, parallel binary Subtractor
Fast Adder - Carry Look Ahead adder
Serial Adder/Subtractor - BCD adder
Binary Multiplier -Multiplexer/ Demultiplexer
decoder - encoder, Magnitude Comparator.
parity checker - parity generators
UNIT 5:
Latches, Design thinking approach of Edge triggered Flip flops SR
Design thinking approach of Edge triggered Flip flops JK
Design thinking approach of Edge triggered Flip flops T, D
Characteristic table and equation, Application table
Design of synchronous counters
